Method for producing interlevel stud vias
US5252516A · kind A · utility
20Cited by
7References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 20, 1992 |
| Grant date | Oct 12, 1993 |
| Priority date | — |
| Expiry date | Feb 20, 2012 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/97
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Metallized level is covered with a relatively thick non-conformal oxide layer, such as sputtered quartz (SiO.sub.2). This layer is, in turn, covered with a relatively thin oxide blanket resistant to RIE, such as aluminum oxide (Al.sub.2 O.sub.3) or Yttrium Oxide (Y.sub.2 O.sub.3). A mask, with exposed via opening, is formed in a conventional manner on the aluminum oxide surface and the aluminum oxide in the open areas is removed, for example Al.sub.2 O.sub.3 is etched with BCl.sub.3 and O.sub.2 gases or wet etch with H.sub.3 PO.sub.4. An RIE process is used to form vias.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.