Du Nguyen
22Patents
15h-index
36Co-inventors
77Inventor score
Filing activity: Feb 20, 1992 → Nov 18, 2010
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6734090B2 | Method of making an edge seal for a semiconductor device | Electricity | 559 | Expired |
| US7397260B2 | Structure and method for monitoring stress-induced degradation of conductive interconnects | Electricity | 167 | Expired |
| US6069068A | Sub-quarter-micron copper interconnections with improved electromigration resistance and reduced defect sensitivity | Electricity | 141 | Expired |
| US6033939A | Method for providing electrically fusible links in copper interconnection | Electricity | 83 | Expired |
| US6130161A | Method of forming copper interconnections with enhanced electromigration resistance and reduced defect sensitivity | Electricity | 66 | Expired |
| US6287954A | Method of forming copper interconnections with enhanced electromigration resistance and reduced defect sensitivity | Electricity | 49 | Expired |
| US6348731B1 | Copper interconnections with enhanced electromigration resistance and reduced defect sensitivity and method of forming same | Electricity | 42 | Expired |
| US5981374A | Sub-half-micron multi-level interconnection structure and process thereof | Electricity | 30 | Expired |
| US6133139A | Self-aligned composite insulator with sub-half-micron multilevel high density electrical interconnections and process thereof | Electricity | 28 | Expired |
| US6069051A | Method of producing planar metal-to-metal capacitor for use in integrated circuits | Emerging Cross-Sectional Technologies | 25 | Expired |
| US6258710A | Sub-quarter-micron copper interconnections with improved electromigration resistance and reduced defect sensitivity | Electricity | 22 | Expired |
| US5252516A | Method for producing interlevel stud vias | Emerging Cross-Sectional Technologies | 20 | Expired |
| US6972209B2 | Stacked via-stud with improved reliability in copper metallurgy | Emerging Cross-Sectional Technologies | 18 | Expired |
| US7279411B2 | Process for forming a redundant structure | Electricity | 17 | Expired |
| US7163883B2 | Edge seal for a semiconductor device | Electricity | 16 | Expired |
| US6294835A | Self-aligned composite insulator with sub-half-micron multilevel high density electrical interconnections and process thereof | Electricity | 14 | Expired |
| US5760595A | High temperature electromigration stress test system, test socket, and use thereof | Physics | 9 | Expired |
| US7138714B2 | Via barrier layers continuous with metal line barrier layers at notched or dielectric mesa portions in metal lines | Electricity | 6 | Expired |
| US6825561B1 | Structure and method for eliminating time dependent dielectric breakdown failure of low-k material | Electricity | 6 | Expired |
| US8466056B2 | Method of forming metal interconnect structures in ultra low-k dielectrics | Electricity | 3 | Active |
| US7639032B2 | Structure for monitoring stress-induced degradation of conductive interconnects | Electricity | 2 | Active |
| US7692439B2 | Structure for modeling stress-induced degradation of conductive interconnects | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.