Method for forming PNP and NPN bipolar transistors in the same substrate
US5254486A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 21, 1992 |
| Grant date | Oct 19, 1993 |
| Priority date | — |
| Expiry date | Feb 21, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0114
Abstract
In one embodiment, this method forms PNP and NPN transistors in a same epitaxial layer. The P-type regions for both the PNP and the NPN transistors are initially defined using a single masking step. Therefore, the emitter and collector region pattern for the PNP transistor is self-aligned with the base region of the NPN transistor. All the defined regions are then doped to achieve a desired base region concentration. A next masking step forms a layer of resist over the base region, and the remainder of the previous masking pattern is retained to define the emitter and collector regions of the PNP transistor. P-type dopants are then implanted in the previously defined emitter and collector regions to form the heavily doped P++ emitter and collector regions of the PNP transistor. Thus, the P++ emitter and collector regions of the PNP transistor will be self-aligned with the P-type base region of the NPN transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.