Fault tolerant, synchronized twin computer system with error checking of I/O communication
US5255367A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 19, 1989 |
| Grant date | Oct 19, 1993 |
| Priority date | — |
| Expiry date | Jul 19, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/88
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dual processor computer system includes a first processing system having a central processing unit which executes a series of data processing instructions, a data bus system for transferring data to and from the first central processing unit, a memory unit coupled to the first central processing unit, and a cross-link communications element for transferring data into and out of the first processing system. A similarly configured second processing system, operating independently of the first processing system, is also provided. The cross-link communications element associated with the second processing system is coupled to the cross-link communication element of the first processing system, for transferring data into the second processing system from the first processing system and for transferring data into the first processing system from the second computer system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.