Electrochemical planarization
US5256565A · kind A · utility
114Cited by
17References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 8, 1989 |
| Grant date | Oct 26, 1993 |
| Priority date | — |
| Expiry date | May 8, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/32115
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a process for fabricating planarized thin film metal interconnects for integrated circuit structures, a planarized metal layer is etched back to the underlying dielectric layer by electropolishing, ion milling or other procedure. Electropolishing reduces processing time from hours to minutes and allows batch processing of multiple wafers. The etched back planarized thin film interconnect is flush with the dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.