Digital testing for high-impedance states in digital electronic circuits
US5256963A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 2, 1990 |
| Grant date | Oct 26, 1993 |
| Priority date | — |
| Expiry date | Nov 2, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/48
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Methods for testing digital electronic device terminals to identify high-impedance states from voltage-defined logic states driven by the digital device being tested. For example, the methods can be used to test a memory chip having a three-state signal terminal. The methods allow for detection of high-impedance states without analog voltage testing, such as by using merely a two-state logic testing apparatus. The methods include precharging the signal terminal to a precharge logic state voltage which is different from a selected logic state voltage. The device being tested is stimulated to produce a test signal state at the signal terminal. If the test state is variable between the high-impedance and the selected state, then maintaining the precharge voltage indicates that the signal terminal is in a high-impedance state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.