Tester calibration verification device
US5256964A · kind A · utility
15Cited by
8References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 31, 1992 |
| Grant date | Oct 26, 1993 |
| Priority date | — |
| Expiry date | Jul 31, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R35/00
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A circuit for verifying the accuracy a tester, for enhancing its calibration and for providing tracking between testers. The circuit includes a delay element, first and second multiplexers connected to the input and output of the delay element, respectively, and a feedback path linking outputs of the second multiplexer to inputs of the first multiplexer to provide an oscillation. The delay between an input of the first multiplexer to an output of the second multiplexer is measured and this delay is compared to the frequency domain measurement of the same to provide an indication of the accuracy of the tester.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.