SAM data selection on dual-ported DRAM devices
US5257237A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 12, 1991 |
| Grant date | Oct 26, 1993 |
| Priority date | — |
| Expiry date | Nov 12, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The selection in a dual port memory device of data from a serial access memory register having a lower byte and an upper byte of data is described herein. In one embodiment, the register is partitioned lengthwise into two sections, corresponding to, for example, a frame buffer A and a frame buffer B. On each serial clock cycle, frame buffer A or frame buffer B for each byte of data may be selected from the register. Each of the selected bytes of data are then passed to a serial output port. In another embodiment, the lower byte of data corresponds to, for example, a frame buffer A and the upper byte corresponds to a frame buffer B. Then either the upper byte or lower byte of data is selected to be output on the serial port. In yet a further embodiment, the serial access memory register is partitioned lengthwise into two sections, each section corresponding to, for example, a frame buffer and the bytes of data correspond to another buffer, then either the lower byte or upper byte is selected to be output on the serial port.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.