Programmable interrupt priority encoder method and apparatus
US5257383A · kind A · utility
11Cited by
19References
8Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 12, 1991 |
| Grant date | Oct 26, 1993 |
| Priority date | — |
| Expiry date | Aug 12, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A programmable, multi-level interrupt priority encoder which fields interrupts from connected devices, e.g., DMA engine, scanner, and timer, and signals an interrupt value, or priority level, associated with that device. These levels, which may range from zero to seven or more, depending upon the system with which it is applied, are used by the CPU to determine which of the plural interrupting devices to service. Using the encoder of the invention, multiple devices can be set at the same priority level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.