Method of forming local etch stop landing pads for simultaneous, self-aligned dry etching of contact vias with various depths
US5258096A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 20, 1992 |
| Grant date | Nov 2, 1993 |
| Priority date | — |
| Expiry date | Aug 20, 2012 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/97
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention introduces the use of "local" etch stop layers having highly selective etch characteristics vis-a-vis insulating layers into which the contact/vias are etched. Any kind of conducting material which possesses etch selectivity to an insulator such as oxide (i.e. doped polysilicon, tungsten, tungsten silicide, titanium, titanium silicide, titanium nitride and the like) may be used and the process flow described herein uses conductively doped polysilicon as an example to accomplish this task without the need to add any extra photo or mask step to a conventional dynamic random access memory (DRAM) process flow and with the addition of a minimal number of deposition and etch steps. During a first masking step to open a contact, a subsequent etch opens up the P-channel gate area to thin down the underlying oxide. Polysilicon is then deposited which is followed by formation of an oxide. During a second masking step the oxide is etched and the polysilicon is etched thereby patterning the polysilicon and creating exposed polysilicon sidewalls. Dielectric isolation is then provided for the polysilicon sidewalls. In a first embodiment nitride spacers are then formed from …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.