Semiconductor memory device having multilayer wiring structure
US5258639A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 4, 1992 |
| Grant date | Nov 2, 1993 |
| Priority date | — |
| Expiry date | Nov 4, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes respective regions of a column decoder and a sense amplifier drive circuit arranged to lie opposite to each other on a semiconductor chip, respective regions of a memory cell array, a column gate and a sense amplifier arranged between the regions of the column decoder and the sense amplifier drive circuit, a plurality of column selection lines led out from the region of the column decoder, connected to respective column gate portions of the region of the column gate, and collected and arranged with units of groups of a predetermined number above the region of the column gate so as to have a smaller arrangement pitch than that of the column gate portion, and at least one sense amplifier drive signal line led out from the region of the sense amplifier drive circuit, connected to respective sense amplifier portions of the region of the sense amplifier, and arranged above the region of the sense amplifier so as to lie next to each group of the column selection lines. By the constitution, it is possible to constitute the memory device without any problem or difficulty from a viewpoint of the layout thereof even if it is a large capacity memory such…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.