Memory cell reading circuit
US5258959A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 19, 1991 |
| Grant date | Nov 2, 1993 |
| Priority date | — |
| Expiry date | Dec 19, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell reading circuit has a reference cell bit line and a matrix cell bit line connected to a supply voltage through respective loads and are furthermore connected by normally-off equalization transistors which are enabled by a first clock signal. The bit lines are further connected by normally-off resistive equalization transistors whose resistance is significant in conducting conditions. The equalization transistors are enabled by a first clock signal and the resistive equalization transistors are enabled by a second clock signal which has a duration that extends longer than the first clock signal. The memory cell reading circuit decreases the "read" time required for a memory cell, such as an EPROM cell, as compared to reading circuits previously used.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.