Method of making a self aligned static induction transistor
US5260227A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 24, 1992 |
| Grant date | Nov 9, 1993 |
| Priority date | — |
| Expiry date | Nov 24, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/012
Abstract
A method of fabricating self aligned static induction transistors. The method comprises fabricating an N silicon on N.sup.- silicon substrate having an active area. A guard ring is formed around the active area. An N.sup.+ polysilicon layer is formed that comprises source and gate regions. An oxide layer is formed on the N.sup.+ polysilicon layer. A second polysilicon layer is formed on the oxide layer. A second oxide layer is formed on the second polysilicon layer which is then masked by a self aligning mask. Trenches are etched into the substrate using the self aligning mask and gate regions are formed at the bottom of the trenches. A first layer of metal (gate metal) is deposited to make contact with the gate regions. A layer of photoresist is deposited and planarized, and the first layer of metal is overetched below the top surface of the trench. Plasma nitride is deposited and planarized, and a polysilicon mask is deposited over the planarized layer of plasma nitride. The polysilicon mask is etched to expose the gate metal disposed on the field. A second layer of metal is deposited to make contact with the source and gate regions. A passivation layer is formed, and interconnec…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.