Boundary-scan input circuit for a reset pin
US5260950A · kind A · utility
27Cited by
16References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 17, 1991 |
| Grant date | Nov 9, 1993 |
| Priority date | — |
| Expiry date | Sep 17, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318555
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A boundary-scan circuit method and apparatus for asserting an internal reset signal connected to core logic circuits of an electronic device in order to assure that testing will begin and end in a safe, known logic state. A safe end state is assured even if the system reset signal on an input pin of the electronic device is logically disconnected from the internal reset connection to the core logic, as often occurs in boundary-scan and related testing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.