Wallace tree multiplier array having an improved layout topology
US5265043A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 27, 1993 |
| Grant date | Nov 23, 1993 |
| Priority date | — |
| Expiry date | Jan 27, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/5338
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A Wallace tree multiplier array (40) performs multiply operations using operands received via a data path (42) having a predetermined height. Rows of carry save adders (CSAs 15'-19") add sets of partial products to generate sets of intermediate summands, which are recursively added to generate a set of final summands. A first group of CSAs form a column which is placed along an axis parallel to the data path (42), and are used to compute a more significant number of bits of each of the summands. The column height of the first group of CSAs is equal to and aligned with the height of the data path (42). A second group of CSAs are placed along an axis perpendicular to the column formed by the first group of CSAs, thereby minimizing the dimension of the multiplier along the data path. The second group of CSAs compute a less significant number of bits of the summands.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.