Ajay Naini
9Patents
6h-index
11Co-inventors
56Inventor score
Filing activity: Nov 4, 1991 → Oct 15, 2004
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7328371B1 | Core redundancy in a chip multiprocessor for highly reliable systems | Physics | 47 | Expired |
| US5220525A | Recoded iterative multiplier | Physics | 34 | Expired |
| US5276635A | Method and apparatus for performing carry look-ahead addition in a data processor | Physics | 17 | Expired |
| US5523961A | Converting biased exponents from single/double precision to extended precision without requiring an adder | Electricity | 12 | Expired |
| US5265043A | Wallace tree multiplier array having an improved layout topology | Physics | 10 | Expired |
| US6603333B2 | Method and apparatus for reduction of noise sensitivity in dynamic logic circuits | Electricity | 6 | Expired |
| US6209083A | Processor having selectable exception handling modes | Physics | 6 | Expired |
| US6954912B2 | Error detection in dynamic logic circuits | Physics | 5 | Expired |
| US6542423B1 | Read port design and method for register array | Physics | 3 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.