High density SRAM circuit with single-ended memory cells
US5265047A · kind A · utility
271Cited by
8References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 9, 1992 |
| Grant date | Nov 23, 1993 |
| Priority date | — |
| Expiry date | Mar 9, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A high density, static random access memory (SRAM) circuit with single-ended memory cells employs a plurality of (4T-2R) or (6T) type SRAM cells and a regenerative sense amplifier. Each of the SRAM cells employs a single bit-line (BL) and two word lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.