Monolithic System Technology, Inc.
70Patents
0Active
70Granted
37Portfolio score
Filing activity: Mar 9, 1992 → Sep 6, 2005
Most-cited patents
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6754746B1 | Memory array with read/write methods | Emerging Cross-Sectional Technologies | 435 | Expired |
| US5829026A | Method and structure for implementing a cache memory using a DRAM array | Physics | 334 | Expired |
| US6913964B2 | Method of fabricating a one transistor floating-body DRAM cell in bulk CMOS process with electrically isolated charge storage region | Electricity | 292 | Expired |
| US6686624B2 | Vertical one-transistor floating-body DRAM cell in bulk CMOS process with electrically isolated charge storage region | Electricity | 285 | Expired |
| US5265047A | High density SRAM circuit with single-ended memory cells | Physics | 271 | Expired |
| US6661042B2 | One-transistor floating-body DRAM cell in bulk CMOS process with electrically isolated charge storage region | Electricity | 229 | Expired |
| US5655113A | Resynchronization circuit for a memory system and method of operating same | Emerging Cross-Sectional Technologies | 219 | Expired |
| US5498990A | Reduced CMOS-swing clamping circuit for bus lines | Emerging Cross-Sectional Technologies | 141 | Expired |
| US5666480A | Fault-tolerant hierarchical bus system and method of operating same | Emerging Cross-Sectional Technologies | 138 | Expired |
| US5592632A | Defect tolerant integrated circuit subsystem for communication between a module and a bus controller in a wafer-scale integrated circuit system | Emerging Cross-Sectional Technologies | 126 | Expired |
| US5843799A | Circuit module redundancy architecture process | Electricity | 118 | Expired |
| US6215497A | Method and apparatus for maximizing the random access bandwidth of a multi-bank DRAM in a computer graphics system | Physics | 114 | Expired |
| US5511020A | Pseudo-nonvolatile memory incorporating data refresh operation | Electricity | 98 | Expired |
| US5498886A | Circuit module redundancy architecture | Electricity | 95 | Expired |
| US5831467A | Termination circuit with power-down mode for use in circuit module architecture | Electricity | 93 | Expired |
| US5613077A | Method and circuit for communication between a module and a bus controller in a wafer-scale integrated circuit system | Emerging Cross-Sectional Technologies | 89 | Expired |
| US6393504B1 | Dynamic address mapping and redundancy in a modular memory device | Emerging Cross-Sectional Technologies | 79 | Expired |
| US5787267A | Caching method and circuit for a memory system with circuit module architecture | Physics | 73 | Expired |
| US6000007A | Caching in a multi-processor computer system | Physics | 66 | Expired |
| US5576554A | Wafer-scale integrated circuit interconnect structure architecture | Electricity | 64 | Expired |
| US6483755B2 | Memory modules with high speed latched sense amplifiers | Emerging Cross-Sectional Technologies | 61 | Expired |
| US6415353B1 | Read/write buffers for complete hiding of the refresh of a semiconductor memory and method of operating same | Physics | 55 | Expired |
| US5729152A | Termination circuits for reduced swing signal lines and methods for operating same | Emerging Cross-Sectional Technologies | 50 | Expired |
| US6256248A | Method and apparatus for increasing the time available for internal refresh for 1-T SRAM compatible devices | Physics | 46 | Expired |
| US6744676B2 | DRAM cell having a capacitor structure fabricated partially in a cavity and method for operating same | Electricity | 44 | Expired |
Source: USPTO / EPO open patent data. Counts and citation impact are objective bibliographic measures.