Chip decoupling capacitor
US5266821A · kind A · utility
77Cited by
8References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 2, 1992 |
| Grant date | Nov 30, 1993 |
| Priority date | — |
| Expiry date | Nov 2, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K1/0231
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An extensive network of N-channel transistor formed capacitor, with one node tie directly to V.sub.cc power bus and the other node directly V.sub.ss power bus, is implemented throughout all open space available on the whole silicon chip (memory as well as logic chip), particularly those directly underneath the metal power bus to achieve an on-chip power bus decoupling capacitor with capacitance in excess of 0.001 .mu.F.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.