Method of forming shallow junctions in field effect transistors
US5268317A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 12, 1991 |
| Grant date | Dec 7, 1993 |
| Priority date | — |
| Expiry date | Nov 12, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/259
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of making a MOS field effect transistor having shallow source and drain regions with improved breakdown and leakage characteristics includes the step of forming a layer of a metal silicide along a surface of a body of silicon at each side of a gate which is on an insulated from the surface. A high concentration of an impurity of a desired conductivity type is implanted only into the metal silicide layers. A lower concentration of the impurity is then implanted through the metal silicide layers and into the body just beneath the metal silicide layers. The body is then annealed at a temperature which drives the impurities from the metal silicide layer into the body to form the junctions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.