Modified silicon CMOS process having selectively deposited Si/SiGe FETS

US5268324A · kind A · utility

Assignee

• International Business Machines Corporation · US

Inventors

• John M. Aitken · South Burlington, US
• Vijay P. Kesan · Croton-on-Hudson, US
• Seshadri Subbanna · Brewster, US
• Manu J. Tejwani · Yorktown Heights, US
• Subramanian S. Iyer · Yorktown Heights, US

Key dates

• Filing date: May 27, 1992
• Grant date: Dec 7, 1993
• Expiry date: May 27, 2012

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S438/902

Abstract

A process is disclosed for making CMOS devices with enhanced performance PMOS FETS by integrating germanium technology into a silicon-based fabrication method. Silicon-germanium layers are selectively grown on the surfaces of oxide-isolated PFET pockets of a silicon substrate previously prepared by a conventional silicon CMOS process. A silicon cap is deposited over each Si--Ge layer and gate insulator is formed over the cap provide gate dielectric for the PFETS. Gate insulator is formed over the NFET pockets to provide gate dielectric for the NFETS. Gate structures are completed along with source and drain junctions in accordance with normal practice. Provision also is made for the additional selective growth of a second silicon-germanium layer on the surfaces of oxide-isolated NFET pockets on the same CMOS substrate to enhance the performance of the NFETS as well as that of the PFETS.