John M. Aitken
23Patents
8h-index
18Co-inventors
72Inventor score
Filing activity: May 27, 1992 → Dec 14, 2016
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5363550A | Method of Fabricating a micro-coaxial wiring structure | Emerging Cross-Sectional Technologies | 77 | Expired |
| US5444015A | Larce scale IC personalization method employing air dielectric structure for extended conductors | Electricity | 57 | Expired |
| US5268324A | Modified silicon CMOS process having selectively deposited Si/SiGe FETS | Emerging Cross-Sectional Technologies | 47 | Expired |
| US5530290A | Large scale IC personalization method employing air dielectric structure for extended conductor | Electricity | 19 | Expired |
| US7381981B2 | Phase-change TaN resistor based triple-state/multi-state read only memory | Electricity | 16 | Expired |
| US6252275A | Silicon-on-insulator non-volatile random access memory device | Electricity | 10 | Expired |
| US7084483B2 | Trench type buried on-chip precision programmable resistor | Electricity | 9 | Expired |
| US6088258A | Structures for reduced topography capacitors | Electricity | 8 | Expired |
| US6352902B1 | Process of forming a capacitor on a substrate | Electricity | 7 | Expired |
| US6159787A | Structures and processes for reduced topography trench capacitors | Electricity | 7 | Expired |
| US7064414B2 | Heater for annealing trapped charge in a semiconductor device | Electricity | 5 | Expired |
| US7943482B2 | Method for semiconductor device having radiation hardened insulators and design structure thereof | Electricity | 3 | Active |
| US7315075B2 | Capacitor below the buried oxide of SOI CMOS technologies for protection against soft errors | Electricity | 3 | Expired |
| US7935609B2 | Method for fabricating semiconductor device having radiation hardened insulators | Electricity | 2 | Active |
| US7601602B2 | Trench type buried on-chip precision programmable resistor | Electricity | 2 | Active |
| US7715248B2 | Phase-change TaN resistor based triple-state/multi-state read only memory | Electricity | 2 | Active |
| US7388274B2 | Capacitor below the buried oxide of SOI CMOS technologies for protection against soft errors | Electricity | 2 | Active |
| US7880158B2 | Phase-change TaN resistor based triple-state/multi-state read only memory | Electricity | 1 | Active |
| US6333239A | Processes for reduced topography capacitors | Electricity | 1 | Expired |
| US7791169B2 | Capacitor below the buried oxide of SOI CMOS technologies for protection against soft errors | Electricity | 0 | Active |
| US11485992B2 | Screening and culture method | Physics | 0 | Active |
| US8035200B2 | Neutralization of trapped charge in a charge accumulation layer of a semiconductor structure | Electricity | 0 | Active |
| US7736915B2 | Method for neutralizing trapped charge in a charge accumulation layer of a semiconductor structure | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.