Process for improving sheet resistance of an integrated circuit device gate
US5268330A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 11, 1992 |
| Grant date | Dec 7, 1993 |
| Priority date | — |
| Expiry date | Dec 11, 2012 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/934
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A passivating layer is deposited over an integrated circuit device, conventionally fabricated using silicidation, after which an insulating layer is deposited. The insulating layer is planarized and further polished to expose the passivating layer above the gate. The portion of the passivating layer above the gate is removed with little or no effect on the insulating layer or gate. A trench above one or both junctions (source or drain) is formed by removing insulation using the passivating layer as an etch stop, then removing a portion of the passivating layer above the junction with little or no effect on the junction or any isolation region present. The gate may be further silicided, and the opening above the gate and the trench above the junction may each be planarly filled with a low sheet resistance conductive material, forming contacts. The contact above the junction may be borderless.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.