Method and apparatus for transferring data within a computer system
US5269005A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 17, 1991 |
| Grant date | Dec 7, 1993 |
| Priority date | — |
| Expiry date | Sep 17, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a processing system any response to an interrupt acknowledge cycle is deferred until the transfer of buffered data to be written from an agent on a subsystem I/O bus to main memory of the system is assured. To expedite system operation, data to be written to main memory by an agent on an I/O bus is buffered in an interface circuit. As soon as the data is buffered, the I/O bus agent is released and interrupts a processor on the system bus indicating completion of the data write. A tightly coupled interrupt controller is used so that the agent does not need to own the I/O or system bus to generate the interrupt. The interrupted processor issues an interrupt acknowledge (IAK) cycle on the system bus to receive an interrupt vector from the interrupt controller. The interface circuit recognizes the IAK cycle and generates a retry signal for the processor if buffered data remains in the interface circuit. In response to the retry signal, the processor is taken off the system bus and not allowed to regain the system bus until the buffered data is written to main memory. A bus busy signal is raised and will not be lowered until the data is written to main memory. When the busy signal is…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.