Edward A. McDonald
22Patents
16h-index
24Co-inventors
77Inventor score
Filing activity: Sep 16, 1991 → Nov 22, 2002
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5676697A | Two-piece, bifurcated intraluminal graft for repair of aneurysm | Human Necessities | 664 | Expired |
| US5728150A | Expandable microporous prosthesis | Human Necessities | 247 | Expired |
| US6090136A | Self expandable tubular support | Human Necessities | 167 | Expired |
| US6120535A | Microporous tubular prosthesis | Human Necessities | 126 | Expired |
| US6292860A | Method for preventing deadlock by suspending operation of processors, bridges, and devices | Physics | 80 | Expired |
| US5359715A | Architectures for computer systems having multiple processors, multiple system buses and multiple I/O buses interfaced via multiple ported interfaces | Physics | 61 | Expired |
| US5269005A | Method and apparatus for transferring data within a computer system | Physics | 30 | Expired |
| US5418914A | Retry scheme for controlling transactions between two busses | Physics | 30 | Expired |
| US6128677A | System and method for improved transfer of data between multiple processors and I/O bridges | Physics | 29 | Expired |
| US6047316A | Multiprocessor computing apparatus having spin lock fairness | Physics | 27 | Expired |
| US6012127A | Multiprocessor computing apparatus with optional coherency directory | Physics | 22 | Expired |
| US6058475A | Booting method for multi-processor computer | Physics | 22 | Expired |
| US6754787B2 | System and method for terminating lock-step sequences in a multiprocessor system | Physics | 22 | Expired |
| US6026472A | Method and apparatus for determining memory page access information in a non-uniform memory access computer system | Physics | 19 | Expired |
| US5758065A | System and method of establishing error precedence in a computer system | Physics | 18 | Expired |
| US5919268A | System for determining the average latency of pending pipelined or split transaction requests through using two counters and logic divider | Physics | 17 | Expired |
| US5701422A | Method for ensuring cycle ordering requirements within a hierarchical bus system including split-transaction buses | Physics | 13 | Expired |
| US5765195A | Method for distributing interprocessor interrupt requests via cache memory coherency mechanisms | Physics | 13 | Expired |
| US6560682B1 | System and method for terminating lock-step sequences in a multiprocessor system | Physics | 12 | Expired |
| US6098113A | Apparatus and method for address translation and allocation for a plurality of input/output (I/O) buses to a system bus | Physics | 11 | Expired |
| US6073216A | System and method for reliable system shutdown after coherency corruption | Physics | 8 | Expired |
| US5327540A | Method and apparatus for decoding bus master arbitration levels to optimize memory transfers | Physics | 7 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.