RISC system capable of simultaneously executing data interlocked shift and arithmetic/logic instructions in one clock cycle by bypassing register
US5269007A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 5, 1990 |
| Grant date | Dec 7, 1993 |
| Priority date | — |
| Expiry date | Nov 5, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3824
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
First and second instructions are simultaneously fetched from a memory to be respectively decoded by first and second instruction decoders. An instruction execution unit includes a register file, an arithmetic and logic unit, and a shifter. A first comparator compares a destination field of the first instruction with a first source field of the second instruction. The shifter produces an output in association with immediate data of the first instruction, the output being ordinarily stored in a register file. However, when both inputs of the comparator are identical to each other, the output from the shifter is supplied to an input of the arithmetic and logic unit via a bypass signal transmission path.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.