Process for filling submicron spaces with dielectric
US5270264A · kind A · utility
111Cited by
1References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 21, 1992 |
| Grant date | Dec 14, 1993 |
| Priority date | — |
| Expiry date | Jul 21, 2012 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/158
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for filling submicron, high aspect ratio gaps, that may have reentrant angles, with a high quality ILD. A first ILD layer is deposited using PECVD to partially fill the gap. Medium-pressure sputter etching is then used to remove the bread-loaf edges and redeposit the etched material in the gaps, thereby allowing small gaps with high aspect ratios and reentrant angles to be completely filled. Finally, a second ILD layer that completely fills the gap is deposited using PECVD.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.