Ebrahim Andideh
70Patents
19h-index
69Co-inventors
87Inventor score
Filing activity: Jul 21, 1992 → Oct 6, 2017
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6437444B2 | Interlayer dielectric with a composite dielectric stack | Electricity | 508 | Expired |
| US5953635A | Interlayer dielectric with a composite dielectric stack | Electricity | 288 | Expired |
| US6765273B1 | Device structure and method for reducing silicide encroachment | Electricity | 232 | Expired |
| US6235568A | Semiconductor device having deposited silicon regions and a method of fabrication | Electricity | 182 | Expired |
| US5270264A | Process for filling submicron spaces with dielectric | Emerging Cross-Sectional Technologies | 111 | Expired |
| US6121100A | Method of fabricating a MOS transistor with a raised source/drain extension | Electricity | 86 | Expired |
| US6506692B2 | Method of making a semiconductor device using a silicon carbide hard mask | Emerging Cross-Sectional Technologies | 81 | Expired |
| US6316063A | Method for preparing carbon doped oxide insulating layers | Chemistry; Metallurgy | 51 | Expired |
| US6624032B2 | Structure and process flow for fabrication of dual gate floating body integrated MOS transistors | Electricity | 51 | Expired |
| US6392271B1 | Structure and process flow for fabrication of dual gate floating body integrated MOS transistors | Electricity | 43 | Expired |
| US5672095A | Elimination of pad conditioning in a chemical mechanical polishing process | Performing Operations; Transporting | 42 | Expired |
| US6362091B1 | Method for making a semiconductor device having a low-k dielectric layer | Electricity | 37 | Expired |
| US6274913A | Shielded channel transistor structure with embedded source/drain junctions | Electricity | 35 | Expired |
| US6777759B1 | Device structure and method for reducing silicide encroachment | Electricity | 32 | Expired |
| US6448185B1 | Method for making a semiconductor device that has a dual damascene interconnect | Electricity | 26 | Expired |
| US6518155B1 | Device structure and method for reducing silicide encroachment | Electricity | 25 | Expired |
| US6350670B1 | Method for making a semiconductor device having a carbon doped oxide insulating layer | Electricity | 24 | Expired |
| US6093651A | Polish pad with non-uniform groove depth to improve wafer polish rate uniformity | Performing Operations; Transporting | 22 | Expired |
| US6417098B1 | Enhanced surface modification of low K carbon-doped oxide | Electricity | 19 | Expired |
| US6482754B1 | Method of forming a carbon doped oxide layer on a substrate | Electricity | 18 | Expired |
| US7755124B2 | Laminating magnetic materials in a semiconductor device | Emerging Cross-Sectional Technologies | 18 | Active |
| US6380010B2 | Shielded channel transistor structure with embedded source/drain junctions | Electricity | 17 | Expired |
| US6191050A | Interlayer dielectric with a composite dielectric stack | Electricity | 15 | Expired |
| US7034380B2 | Low-dielectric constant structure with a multilayer stack of thin films with pores | Electricity | 14 | Expired |
| US6677253B2 | Carbon doped oxide deposition | Electricity | 14 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.