Method for optimum erasing of EEPROM
US5270979A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 15, 1991 |
| Grant date | Dec 14, 1993 |
| Priority date | — |
| Expiry date | Mar 15, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1008
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Various optimizing techniques are used for erasing semiconductor electrically erasable programmable read only memories (EEPROM). An erase algorithm accomplishes erasing of a group of memory cells by application of incremental erase pulses. Techniques include a 2-phase verification process interleaving between pulse applications; special handling of a sample of cells within each erasable unit group; defects handling; adaptive initial erasing voltages; and single-and hybrid-phase algorithms with sector to sector estimation of erase characteristics by table lookup. Techniques are also employed for controlling the uniformity of program/erase cycling of cells in each erasable unit group. Defects handling includes an adaptive data encoding scheme.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.