Level shifter circuit
US5272389A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 29, 1992 |
| Grant date | Dec 21, 1993 |
| Priority date | — |
| Expiry date | Apr 29, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356113
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A level shifter circuit includes first and second inverter circuits comprising first and second PMOS transistor and an NMOS transistor which are connected in series between a point of first potential V.sub.LC and a point of ground potential, connections interconnecting the output nodes of the respective ones of the inverter circuits to the gates of the second PMOS transistors of the respective other inverter circuits, an input signal circuit for providing to the inverter circuits respective input signals Sa, Sb which changes in a substantially complementary manner between a second potential V.sub.DD and ground potential, and a level setting circuit for forcibly setting the respective output nodes of the inverter circuits to the second potential V.sub.DD when a signal applied to said input signal circuit changes. The second potential V.sub.DD is equal to or less than the first potential V.sub.LC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.