Integrated circuit package having an internal cavity for incorporating decoupling capacitor
US5272590A · kind A · utility
Inventor
Key dates
| Filing date | Feb 12, 1990 |
| Grant date | Dec 21, 1993 |
| Priority date | — |
| Expiry date | Feb 12, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30107
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A decoupling scheme is presented which is particularly well suited for use with integrated circuit packages having internal cavities for receiving an integrated circuit chip such as Pin Grid Array (PGA) packages, ceramic dual-in-line packages, ceramic flat packs and ceramic leadless chip carriers. In accordance with the present invention, a decoupling capacitor (which preferably comprises a very thin high capacitance layer made by a thick film or thin film process sandwiched between an inner and outer electrode layer) is positioned within the internal cavity of an integrated circuit package such as a PGA package and electrically connected to the IC chip within the cavity. In a particularly preferred embodiment, the decoupling capacitor has a novel configuration for improved heat transfer. This novel configuration includes a pair of parallel plate electrodes wherein the upper electrode has extended flaps which wrap around the top surface of the decoupling capacitor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.