Method of manufacture transistor having gradient doping during lateral epitaxy
US5273929A · kind A · utility
8Cited by
8References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 19, 1991 |
| Grant date | Dec 28, 1993 |
| Priority date | — |
| Expiry date | Aug 19, 2011 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/933
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A power transistor comprises, on a layer of insulator, a layer of a semiconductor material comprising several zones with N+, N and N+ doping. The N doped zone corresponds to the gate zone. The N+ doped zones correspond to the drain and source zones. A method for the making of such a transistor is also disclosed. Application: the making of a field-effect transistor with improved heat dissipation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.