Multichip module having SiO.sub.2 insulating layer
US5274270A · kind A · utility
51Cited by
17References
6Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 22, 1993 |
| Grant date | Dec 28, 1993 |
| Priority date | — |
| Expiry date | Jan 22, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K1/16
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multichip module for interconnecting a plurality of integrated circuits. A thick layer of silicon dioxide, up to 20 .mu.m, serves as a dielectric to separate metal signal layers from power and ground planes The silicon dioxide layer is deposited to have a residual compressive stress of less than 2.times.10.sup.9 dynes/cm.sup.2, and preferably less than 1.times.10.sup.9 dynes/cm.sup.2, to prevent cracking.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.