Output driver circuit comprising a programmable circuit for determining the potential at the output node and the method of implementing the circuit
US5274276A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 26, 1992 |
| Grant date | Dec 28, 1993 |
| Priority date | — |
| Expiry date | Jun 26, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00384
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The invention is an output driver circuit of a dynamic random access memory (DRAM) wherein the output driver is wired in a push-pull configuration. The push-pull configuration comprises a pull-up portion and a pull-down portion serially connected at an output node. The pull-up portion comprises a an n-channel metal oxide semiconductor (NMOS) transistor having a gate potential determined by a programmable circuit. In the preferred embodiment the programmable circuit provides a potential to the gate node of the NMOS that is directly proportional to the supply potential until a maximum programmed gate potential is reached. The programmable circuit maintains the maximum programmed gate potential for further increases in the supply potential. The pull-down portion comprises a pull-down NMOS transistor interposed between the output node and ground. The pull-down NMOS transistor is controlled by a pull-down signal on the gate node. When actuated the pull-down transistor provides a low logic level at the output node. The invention is also the method of driving a potential to the output node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.