Semiconductor integrated circuit having a stand-by current reducing circuit
US5274601A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Nov 6, 1992 |
| Grant date | Dec 28, 1993 |
| Priority date | — |
| Expiry date | Nov 6, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A device parameter of a switching transistor is set in such a way that a leakage current of the switching transistor making up a power source switch which is turned off in a stand-by state is smaller than the sum total of subthreshold currents of P-channel or N-channel MOS transistors in an off state of a plurality of CMOS circuits. Therefore, the currents which flow through the plurality of CMOS circuits in the stand-by state are not determined by the subthreshold current but are determined by a small leakage current of the switching transistor. As a result, even when the CMOS circuit is shrunken and the subthreshold current increases, it is possible to reduce the current consumption in the stand-by state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.