Clock switching apparatus and method for computer systems
US5274678A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 30, 1991 |
| Grant date | Dec 28, 1993 |
| Priority date | — |
| Expiry date | Dec 30, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0083
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A clock switching apparatus is provided in a data processing system which includes a system clock for selectively switching the system clock from a first clock signal to a second clock signal and vice versa. The clock switching apparatus includes a multiplexer coupled to receive the first clock signal and the second clock signal for selectively switching the system clock from the first clock signal to the second clock signal. The multiplexer provides the system clock. A control logic circuit is coupled to receive the second clock signal and a control signal for controlling the multiplexer to switch the system clock from the first clock signal to the second clock signal, wherein the control signal is synchronized to the second clock signal in the control logic circuit to become a synchronized control signal. The multiplexer switches the system clock from the first clock signal to the second clock signal when receiving the synchronized control signal from the control logic circuit. A pass logic circuit is provided for outputting the system clock. The pass logic circuit receives the system clock from the multiplexer. The pass logic circuit is controlled by the control logic circuit to…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.