Hybrid open folded sense amplifier architecture for a memory device
US5276641A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 12, 1991 |
| Grant date | Jan 4, 1994 |
| Priority date | — |
| Expiry date | Dec 12, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4096
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A hybrid open/folded bit line sense amplifier arrangement and accompanying circuitry primarily for use on a ULSI DRAM memory chip to reduce the area needed for a memory cell and eliminate noise between bit lines. The circuitry includes two memory arrays containing a plurality of memory cells interconnected by a plurality of bit lines and word lines. In the preferred embodiment, the memory cells are accessible on every two out of three bit lines encountered by a word line. A set of open bit line sense amplifiers each with two connectors, one multiplexed to a number of bit lines in the first array and the other multiplexed to a number of bit lines in the second array is provided. Each memory array has a set of folded bit line sense amplifiers with two connectors each connector multiplexed to a number of bit lines in the array. The control circuitry with multiplexing ensures that the connectors of the sense amplifiers access only one bit lines at a time. The accessed by the connectors of each folded line sense amplifier are non-adjacent and simultaneously therewith, a connector of an open bit sense amplifier accesses a bit line between the bit lines accessed by the folded sense amplif…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.