Spare memory arrangement
US5276834A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 4, 1990 |
| Grant date | Jan 4, 1994 |
| Priority date | — |
| Expiry date | Dec 4, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1044
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A spare memory arrangement in which a defective chip in a memory array can be electronically replaced with a spare chip of identical construction. A defective memory chip is first detected and located by a suitable means, such as an error correction code (ECC), check sum, or parity check. A sparer chip is constructed to be actuated upon a read to the defective memory chip to replace the defective chip with a memory spare chip. The sparer chip includes a cross-point memory (CPM) cell having an address register for receiving data from a central processing unit (CPU) and routing the data to and from the spare memory chip. The cross-point memory (CPM) cell is actuated by control input from the (CPU).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.