Method for forming grain boundary junction devices using high T.sub.c superconductors
US5278140A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 16, 1992 |
| Grant date | Jan 11, 1994 |
| Priority date | — |
| Expiry date | Sep 16, 2012 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S505/728
Abstract
A method is disclosed for fabricating grain boundary junction devices, which comprises preparing a crystalline substrate containing at least one grain boundary therein, epitaxially depositing a high Tc superconducting layer on the substrate, patterning the superconducting layer to leave at least two superconducting regions on either side of the grain boundary and making electrical contacts to the superconducting regions so that bias currents can be produced across the grain boundary.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.