Temperature-dependent DRAM refresh circuit
US5278796A · kind A · utility
205Cited by
2References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 12, 1991 |
| Grant date | Jan 11, 1994 |
| Priority date | — |
| Expiry date | Apr 12, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/406
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A temperature sensing circuit allows a DRAM array to use less power than would normally be possible due to the reduced refresh rate based on the temperature of the DRAM array. The temperature circuit removes the refresh guardbanding on the DRAMS. Instead of refreshing a 1 megabyte DRAM every 8 ms, refreshing the DRAMs every 128 ms is possible, depending on the temperature of the DRAM array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.