Apparatus and method for data induced condition signalling
US5278840A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 15, 1993 |
| Grant date | Jan 11, 1994 |
| Priority date | — |
| Expiry date | Jan 15, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/8053
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a data processing system, an instruction is disclosed that generates a fault when a predetermined register position (e.g., the low or least significant bit position) has a predetermined logic signal (e.g., a logic `0` signal). This instruction provides a mechanism to determine when a Boolean value indicates a presence of a fault condition and provides a mechanism to generate the fault when present. For example, in arrays of memory locations that can be addressed by a program, this instruction can respond to the presence of an array address (or reference) that is outside the prescribed bounds of the array. When an invalid address is identified, a signal is entered in the low (i.e., least significant) bit position of a processor scalar register. The instruction repertoire includes a Fault on Low Bit Clear instruction that tests the contents of the scalar register low bit position, and when a logic `0` signal is found therein, an exception signal is generated and applied to the control program of the data processing system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.