Look-ahead asynchronous register set/reset in programmable logic device
US5280203A · kind A · utility
31Cited by
4References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 15, 1992 |
| Grant date | Jan 18, 1994 |
| Priority date | — |
| Expiry date | May 15, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17792
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable logic device in which macrocell register reset time, T.sub.clear, and set time, T.sub.set, are comparable in speed to the combinatorial propagation delay time, T.sub.pd. In setting or resetting the macrocell register, the Set (Reset) signal is applied simultaneously to a clocked master latch in the macrocell register and to an output node. During the Set (Reset) period the slave latch of the macrocell register is disconnected from the output node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.