High speed fail processor
US5280486A · kind A · utility
14Cited by
4References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 8, 1993 |
| Grant date | Jan 18, 1994 |
| Priority date | — |
| Expiry date | Feb 8, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31919
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An apparatus for processing failure information received from a node of a circuit under test. The apparatus includes a fail processor which receives test data from a node and generates failure data based upon the test data, a plurality of fail memories, each memory being configured to receive and store certain fail data, and a sequence memory configured-to store sequence information indicating in what order the failure data is stored in the plurality of fail memories.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.