Slip detection during bit-error-rate measurement
US5282211A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 15, 1991 |
| Grant date | Jan 25, 1994 |
| Priority date | — |
| Expiry date | Oct 15, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/241
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A bit-error-rate detector (20) in a test set (10) for a frame-based communications channel employs a pseudo-random-number generator (46) at the channel's output end that generates a sequence the same as that produced by a pseudo-random-number generator (16) at the input end, but typically with a timing offset. A chain of delay circuits (38, 40, 42, and 44) receives the channel output. Each delay circuit imposes a delay equal to a single frame time and produces a respective output. One such output (CENTER) is normally compared in an XOR gate (52) with the output of the output-end pseudo-random-number generator (46). The XOR gate (52) applies signals indicative of any symbol mismatches to a shift register (88), which forwards them, after a delay, to a bit-error-rate counter (90). At the same time, another XOR GATE (70) compares the output of the channel or of one of the other delay circuits (38, 42, and 44) with the pseudo-random-number-generator output, and a decoder (80) generates a slip-indicating output when a counter (76), which counts the number of consecutive matches that the latter XOR GATE (70) detects, indicates that the output of the channel or other delay circuit (38, 42,…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.