Translation of multiple virtual pages upon a TLB miss
US5282274A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 24, 1990 |
| Grant date | Jan 25, 1994 |
| Priority date | — |
| Expiry date | May 24, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/684
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatus, and accompanying methods for use therein, for translating virtual page addresses in one address space, e.g. virtual, to page addresses in a second address space, e.g. real, and specifically for increasing the speed of such translations by translating multiple contiguous virtual page addresses upon the occurrence of a miss in a translation lookaside buffer (TLB). In response to a TLB miss, the address of each virtual page in a pre-defined block of, e.g. four, contiguous virtual pages, is separately translated through segment and/or page table lookup operations to yield corresponding page frame addresses. The virtual and corresponding page frame addresses for this block are then stored within a single TLB entry. Inasmuch as successive virtual page addresses can be constructed through simple incrementation of a starting virtual page address for this block, a TLB entry contains the first virtual page address for the block followed by the separate page frame address, and its associated invalid and page protection bit fields, for each of the contiguous virtual pages in that block. Since segment and block values are the same for all the page frame addresses in each block, these…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.