Non-volatile semiconductor memory device
US5283758A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 20, 1991 |
| Grant date | Feb 1, 1994 |
| Priority date | — |
| Expiry date | Nov 20, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0491
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A plurality of memory cell transistors having floating gates are disposed in a matrix in the direction of row and column to form a memory cell array. The memory cell array is divided into a plurality of sectors for every predetermined row. In each sector, sector selecting transistors and sub bit lines are provided, so that erasing and programming can be made for each sector. Therefore, total erasing for sector becomes possible, and since no voltage is applied to sub bit lines and word lines of non-selected sectors, the number of operations of preventing writing into non-selected memory cells is as many as the word lines included in one sector.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.