Multi-processor programmable interrupt controller system
US5283904A · kind A · utility
354Cited by
15References
18Claims
0Family size
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Key dates
| Filing date | Jan 22, 1993 |
| Grant date | Feb 1, 1994 |
| Priority date | — |
| Expiry date | Jan 22, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/17
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-processor programmable interrupt controller system which includes: an I/O interrupt controller for receiving interrupt requests from an I/O subsystem; multiple processor interrupt controllers, each associated with a specific processor for dispensing of accepted interrupts; and an interrupt controller bus primarily for the transmission of interrupt requests between interrupt controller units and for priority arbitration, using a standard message format and arbitration protocol.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.