Bi-layer resist process for semiconductor processing

US5286607A · kind A · utility

Assignee

• Chartered Semiconductor Manufacturing LTD · SG

Inventor

• Andrew Brown · San Jose, US

Key dates

• Filing date: Dec 9, 1991
• Grant date: Feb 15, 1994
• Expiry date: Dec 9, 2011

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S438/95
• WIPO field: Optics
• WIPO sector: Instruments

Abstract

A multi-level patterning process for use in the semiconductor fabrication technology that will consistently produce a very fine and well defined pattern, and which can be re-worked, especially at the early stages of the process is accomplished. In the process, a thick resist, such as a Novolak resin with suitable additives is spun on a wafer. This material is heavily dyed to the exposing wave length of the radiant energy source of the stepper. The planerizing layer is exposed to a silicon containing atmosphere, such as hexamethyldisilazane (HMDS) for a period of time and a temperature sufficient for the silicon to penetrate a short distance, for example about 0.25 micrometers into the resist. The resist is crosslinked during this bake or during a subsequent bake. These wafers are now ready for standard resist processing. The resist is spun, exposed, and developed. The wafers are then inspected for error. Rework can be accomplished at the stage by stripping the top resist and recoating. After inspection, the wafers go through a short RIE that transfers the pattern down through the silicon containing layer. This etch is then converted to an oxygen gas only etch that etches the rest o…