Memory cell circuit and array
US5287304A · kind A · utility
11Cited by
4References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 31, 1990 |
| Grant date | Feb 15, 1994 |
| Priority date | — |
| Expiry date | Dec 31, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/412
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An improved memory cell (118) is provided which may be incorporated into an array (202) of memory cells. Array (202) includes a first gate conductor region (224) and a second gate conductor region (238), wherein the first and second gate conductor regions are orthogonal to one another. Each one-half of the cell may include two series transistors connected to a cross-coupled trench transistor. Cross-coupling of the trench transistors is effected through the use of parallel local interconnect regions (256) and (258).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.