System and method for drawing antialiased polygons
US5287438A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 13, 1992 |
| Grant date | Feb 15, 1994 |
| Priority date | — |
| Expiry date | Aug 13, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T15/503
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system (30) draws antialiased polygons. A CPU (32) is connected to a floating point processor (FPU) (34) by bus (36). The CPU (32) is connected by a 32-bit system bus (38) to a random access memory (RAM) (40), a cache (42) and an interface (44) in graphics subsystem (45). The interface (44) is connected by bus (46) to graphics processor (48). The graphics processor (48) is connected by 120-bit graphics bus (50) to frame buffer (52). The frame buffer (52) is connected to a video digital to analog converter (DAC) (54) by bus (56). The DAC (54) is connected to video display (58) by line (60). The graphics processor (48) use a technique known as super-sampling to combat the effects of aliasing. In aliased mode, the graphics processor (48) use 16 array sites to sample 16 pixels (72). When drawing a polygon or line in antialiased mode, the graphics processor (48) uses the 16 sites to sample at 16 locations (120) within a single pixel (72). The antialiasing is done by determining what proportion of the locations (120) within each pixel (72) are within the polygon and setting a color of each pixel (72) on the basis of the proportion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.